Design Rule Verification Report

Date:		12/06/2026
Time:		11:56:10
Elapsed Time:		00:00:00
Filename:		C:\Users\Jacob-\Documents\- Group Project\Greenhouse Central Management System\PCB1.PcbDoc

Warnings:		0
Rule Violations:		66

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0mm) (InNet('No Net')),(OnLayer('Keep-Out Layer'))	0
Clearance Constraint (Gap=0mm) (InNet('No Net')),(InNet('No Net'))	0
Clearance Constraint (Gap=0.254mm) (All),(All)	8
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	13
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.35mm) (InNet('NetDeHumid_1'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.35mm) (InNet('+12'))	0
Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.35mm) (InNet('NetHumidif_1'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.254mm) (InNet('NetK3_3'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.254mm) (InNet('NetK2_3'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.254mm) (InNet('NetK1_3'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.3mm) (InNet('+5'))	0
Width Constraint (Min=0.254mm) (Max=0.4mm) (Preferred=0.35mm) (InNet('+12'))	0
Routing Topology Rule(Topology=Shortest) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)	3
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	6
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)	7
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)	10
Silk to Silk (Clearance=0.254mm) (All),(All)	19
Net Antennae (Tolerance=0mm) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	66

Clearance Constraint (Gap=0.254mm) (All),(All)
Clearance Constraint: (0.181mm < 0.254mm) Between Arc (78.859mm,25.814mm) on Keep-Out Layer And Via (79.867mm,25.423mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.221mm < 0.254mm) Between Arc (78.859mm,25.814mm) on Keep-Out Layer And Via (79.894mm,26.244mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.212mm < 0.254mm) Between Arc (82.296mm,25.843mm) on Keep-Out Layer And Via (81.263mm,25.432mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.187mm < 0.254mm) Between Arc (82.296mm,25.843mm) on Keep-Out Layer And Via (81.29mm,26.253mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.099mm < 0.254mm) Between Track (28.372mm,26.543mm)(122.758mm,26.543mm) on Keep-Out Layer And Via (79.894mm,26.244mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.095mm < 0.254mm) Between Track (28.372mm,26.543mm)(122.758mm,26.543mm) on Keep-Out Layer And Via (80.358mm,26.248mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.087mm < 0.254mm) Between Track (28.372mm,26.543mm)(122.758mm,26.543mm) on Keep-Out Layer And Via (80.809mm,26.256mm) from Top Layer to Bottom Layer
Clearance Constraint: (0.09mm < 0.254mm) Between Track (28.372mm,26.543mm)(122.758mm,26.543mm) on Keep-Out Layer And Via (81.29mm,26.253mm) from Top Layer to Bottom Layer

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net +5 Between Pad P2 ^-1(86.614mm,23.368mm) on Multi-Layer And Track (92.964mm,28.194mm)(95.25mm,30.48mm) on Top Layer
Un-Routed Net Constraint: Net PB3 Between Pad P2 ^-2(84.074mm,23.368mm) on Multi-Layer And Track (90.424mm,28.194mm)(90.424mm,30.988mm) on Top Layer
Un-Routed Net Constraint: Net GND Between Pad P2 ^-3(81.534mm,23.368mm) on Multi-Layer And Pad P3 .-5(82.931mm,28.067mm) on Multi-Layer
Un-Routed Net Constraint: Net PB2 Between Pad SW3-1(82.895mm,17.855mm) on Multi-Layer And Pad P3 .-4(85.471mm,28.067mm) on Multi-Layer
Un-Routed Net Constraint: Net PB1 Between Track (73.418mm,22.267mm)(73.914mm,22.763mm) on Top Layer And Track (80.264mm,28.194mm)(83.439mm,31.369mm) on Top Layer
Un-Routed Net Constraint: Via (79.867mm,25.423mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (79.894mm,26.244mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (80.33mm,25.427mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (80.358mm,26.248mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (80.782mm,25.435mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (80.809mm,26.256mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (81.263mm,25.432mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.
Un-Routed Net Constraint: Via (81.29mm,26.253mm) from Top Layer to Bottom Layer Dead Copper - Net Not Assigned.

Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (3.5mm > 2.54mm) Pad J1-1(34.394mm,72.263mm) on Multi-Layer Actual Slot Hole Width = 3.5mm
Hole Size Constraint: (3mm > 2.54mm) Pad J1-2(28.194mm,72.263mm) on Multi-Layer Actual Slot Hole Width = 3mm
Hole Size Constraint: (3mm > 2.54mm) Pad J1-3(31.194mm,67.563mm) on Multi-Layer Actual Slot Hole Width = 3mm

Hole To Hole Clearance (Gap=0.254mm) (All),(All)
Hole To Hole Clearance Constraint: (0.163mm < 0.254mm) Between Via (79.867mm,25.423mm) from Top Layer to Bottom Layer And Via (80.33mm,25.427mm) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (0.163mm < 0.254mm) Between Via (79.894mm,26.244mm) from Top Layer to Bottom Layer And Via (80.358mm,26.248mm) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (0.152mm < 0.254mm) Between Via (80.33mm,25.427mm) from Top Layer to Bottom Layer And Via (80.782mm,25.435mm) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (0.152mm < 0.254mm) Between Via (80.358mm,26.248mm) from Top Layer to Bottom Layer And Via (80.809mm,26.256mm) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (0.181mm < 0.254mm) Between Via (80.782mm,25.435mm) from Top Layer to Bottom Layer And Via (81.263mm,25.432mm) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (0.181mm < 0.254mm) Between Via (80.809mm,26.256mm) from Top Layer to Bottom Layer And Via (81.29mm,26.253mm) from Top Layer to Bottom Layer

Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.12mm < 0.254mm) Between Pad R1-2(37.58mm,49.276mm) on Top Layer And Via (38.735mm,49.276mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.12mm]
Minimum Solder Mask Sliver Constraint: (0.163mm < 0.254mm) Between Via (79.867mm,25.423mm) from Top Layer to Bottom Layer And Via (80.33mm,25.427mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.163mm] / [Bottom Solder] Mask Sliver [0.163mm]
Minimum Solder Mask Sliver Constraint: (0.163mm < 0.254mm) Between Via (79.894mm,26.244mm) from Top Layer to Bottom Layer And Via (80.358mm,26.248mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.163mm] / [Bottom Solder] Mask Sliver [0.163mm]
Minimum Solder Mask Sliver Constraint: (0.152mm < 0.254mm) Between Via (80.33mm,25.427mm) from Top Layer to Bottom Layer And Via (80.782mm,25.435mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.152mm] / [Bottom Solder] Mask Sliver [0.152mm]
Minimum Solder Mask Sliver Constraint: (0.152mm < 0.254mm) Between Via (80.358mm,26.248mm) from Top Layer to Bottom Layer And Via (80.809mm,26.256mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.152mm] / [Bottom Solder] Mask Sliver [0.152mm]
Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Via (80.782mm,25.435mm) from Top Layer to Bottom Layer And Via (81.263mm,25.432mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm] / [Bottom Solder] Mask Sliver [0.181mm]
Minimum Solder Mask Sliver Constraint: (0.181mm < 0.254mm) Between Via (80.809mm,26.256mm) from Top Layer to Bottom Layer And Via (81.29mm,26.253mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.181mm] / [Bottom Solder] Mask Sliver [0.181mm]

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (44.704mm,63.499mm) on Top Overlay And Pad C4-1(44.704mm,62.624mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (44.704mm,63.499mm) on Top Overlay And Pad C4-1(44.704mm,62.624mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (48.133mm,73.278mm) on Top Overlay And Pad C3-1(48.133mm,72.403mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (48.133mm,73.278mm) on Top Overlay And Pad C3-1(48.133mm,72.403mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (68.071mm,50.8mm) on Top Overlay And Pad C5-1(67.196mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (68.071mm,50.8mm) on Top Overlay And Pad C5-1(67.196mm,50.8mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (72.262mm,31.242mm) on Top Overlay And Pad C6-1(71.387mm,31.242mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Arc (72.262mm,31.242mm) on Top Overlay And Pad C6-1(71.387mm,31.242mm) on Top Layer [Top Overlay] to [Top Solder] clearance [0.25mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad K3-3(101.66mm,56.47mm) on Multi-Layer And Text "U1" (101.727mm,54.737mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R8-1(57.023mm,60.96mm) on Multi-Layer And Text ".Designator" (57.301mm,60.325mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]

Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.081mm < 0.254mm) Between Arc (117.885mm,62.738mm) on Top Overlay And Text "Light" (117.427mm,61.417mm) on Top Overlay Silk Text to Silk Clearance [0.081mm]
Silk To Silk Clearance Constraint: (0.102mm < 0.254mm) Between Arc (117.885mm,69.85mm) on Top Overlay And Text "DeHumid" (117.467mm,67.617mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
Silk To Silk Clearance Constraint: (0.041mm < 0.254mm) Between Arc (117.885mm,76.962mm) on Top Overlay And Text "Humidif" (117.467mm,75.36mm) on Top Overlay Silk Text to Silk Clearance [0.041mm]
Silk To Silk Clearance Constraint: (0.105mm < 0.254mm) Between Arc (118.012mm,34.29mm) on Top Overlay And Text "W Pump" (117.808mm,32.728mm) on Top Overlay Silk Text to Silk Clearance [0.105mm]
Silk To Silk Clearance Constraint: (0.169mm < 0.254mm) Between Arc (118.012mm,48.514mm) on Top Overlay And Text "Cooler" (117.467mm,46.991mm) on Top Overlay Silk Text to Silk Clearance [0.169mm]
Silk To Silk Clearance Constraint: (0.168mm < 0.254mm) Between Arc (118.012mm,55.626mm) on Top Overlay And Text "Heater" (117.467mm,54.357mm) on Top Overlay Silk Text to Silk Clearance [0.168mm]
Silk To Silk Clearance Constraint: (0.211mm < 0.254mm) Between Arc (68.071mm,50.8mm) on Top Overlay And Text "C5" (68.509mm,50.427mm) on Top Overlay Silk Text to Silk Clearance [0.211mm]
Silk To Silk Clearance Constraint: (0.211mm < 0.254mm) Between Arc (68.071mm,50.8mm) on Top Overlay And Text "C5" (68.509mm,50.427mm) on Top Overlay Silk Text to Silk Clearance [0.211mm]
Silk To Silk Clearance Constraint: (0.185mm < 0.254mm) Between Arc (94.33mm,19.305mm) on Top Overlay And Text "SW4" (91.25mm,19.185mm) on Top Overlay Silk Text to Silk Clearance [0.185mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (44.272mm,64.364mm) on Top Overlay And Track (41.43mm,64.523mm)(46.03mm,64.523mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (44.272mm,64.364mm) on Top Overlay And Track (45.53mm,64.523mm)(45.53mm,74.923mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "C4" (44.272mm,64.364mm) on Top Overlay And Track (46.03mm,64.523mm)(46.03mm,74.923mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "K1" (66.675mm,77.089mm) on Top Overlay And Track (67.405mm,69.043mm)(67.405mm,80.643mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.035mm < 0.254mm) Between Text "P2 ^" (73.306mm,20.836mm) on Top Overlay And Track (72.454mm,22.098mm)(88.074mm,22.098mm) on Top Overlay Silk Text to Silk Clearance [0.035mm]
Silk To Silk Clearance Constraint: (0.162mm < 0.254mm) Between Text "P3 ." (80.033mm,29.726mm) on Top Overlay And Track (78.931mm,29.337mm)(94.551mm,29.337mm) on Top Overlay Silk Text to Silk Clearance [0.162mm]
Silk To Silk Clearance Constraint: (0.245mm < 0.254mm) Between Text "R3" (91.877mm,53.348mm) on Top Overlay And Track (85.341mm,54.82mm)(95.641mm,54.82mm) on Top Overlay Silk Text to Silk Clearance [0.245mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "U1" (101.727mm,54.737mm) on Top Overlay And Track (100.26mm,54.82mm)(110.56mm,54.82mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.228mm < 0.254mm) Between Text "U2" (38.735mm,36.449mm) on Top Overlay And Track (41.73mm,34.444mm)(41.73mm,47.344mm) on Top Overlay Silk Text to Silk Clearance [0.228mm]
Silk To Silk Clearance Constraint: (0.069mm < 0.254mm) Between Text "W Pump" (117.808mm,32.728mm) on Top Overlay And Track (118.437mm,32.85mm)(118.437mm,38.27mm) on Top Overlay Silk Text to Silk Clearance [0.069mm]